Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET or MOS), in which a gate is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-channel and p-channel (NMOS and PMOS) transistors are used to fabricate logic and other circuitry.
The source and drain are typically formed by adding dopants to targeted regions of a semiconductor body on either side of the channel. A gate structure is formed above the channel, having a gate dielectric formed over the channel and a gate electrode above the gate dielectric. The gate dielectric is an insulator material, which prevents large currents from flowing into the channel when a voltage is applied to the gate electrode, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. Conventional MOS transistors typically include a gate dielectric formed by depositing or growing silicon dioxide (SiO2) over a silicon wafer surface, with doped polysilicon formed over the SiO2 to act as the gate electrode.
Continuing trends in semiconductor device manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface. However, there are electrical and physical limitations on the extent to which thickness of SiO2 gate dielectrics can be reduced. For example, very thin SiO2 gate dielectrics are prone to large gate tunneling leakage currents resulting from direct tunneling through the thin gate oxide. In addition, there are conventional limitations on the ability to form such thin oxide films with uniform thickness. Furthermore, thin SiO2 gate dielectric layers provide a poor diffusion barrier to dopants, for example, and may allow high boron dopant penetration into the underlying channel region of the silicon during fabrication of the source/drain regions.
Recent MOS transistor scaling efforts have accordingly focused on high-k dielectric materials having dielectric constants greater than that of SiO2 (e.g., greater than about 3.9), which can be formed in a thicker layer than scaled SiO2, and yet which produce equivalent field effect performance. The relative electrical performance of such high-k dielectric materials is often expressed as equivalent oxide thickness (EOT), because the high-k material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2. Since the dielectric constant “k” is higher than that of silicon dioxide, a thicker high-k dielectric layer can be employed to mitigate tunneling leakage currents, while still achieving the equivalent electrical performance of a thinner layer of thermally grown SiO2, nitrided SiO2, or SiON.
The performance and reliability of the resulting MOS transistors is dependent upon the quality of the high-k gate dielectric material, including the bulk high-k material and also the quality of the interface region between the high-k gate dielectric material and the underlying silicon. Unlike SiO2, which may be formed by thermal oxidation (growth process), high-k dielectrics are typically deposited over the semiconductor substrate, using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or other deposition processes. While the macroscopic composition (e.g., stoichiometry) of these materials may be controlled to a certain extent during such deposition processes, stoichiometric composition variations within the film may degrade device performance.
In addition, the above deposition techniques often create high-k dielectric films having point defects that affect transistor performance. Such defects may include oxygen vacancies, and/or other point defects affecting leakage through the gate dielectric. Furthermore, certain deposition processes (e.g., CVD, ALD, etc.) may introduce impurities (e.g. Cl, C, OH, H, etc.) into the deposited high-k dielectric film, which also degrade device performance. Moreover, the deposited film may not be of optimal density, wherein sub par performance may result. Accordingly, there is a need for improved gate dielectric fabrication techniques by which high quality gate dielectrics and interfaces can be achieved.